1. Field of the Invention
The present invention relates to an apparatus and a method for analyzing C-V (Capacitance-Voltage) characteristics of a MIS (Metal/Insulator/Semiconductor) structure, and more particularly to an apparatus and a method which can analyze C-V characteristics of a MIS structure including a thin film silicon oxide having the thickness of less than 3 nm.
2. Description of the Related Art
Conventionally, in the case where a logic circuit provided in a semiconductor integrated circuit includes devices a threshold voltage of which is low so as to operate the semiconductor integrated circuit at a low voltage, there is a problem that a leakage current in the semiconductor integrated circuit is increased when the semiconductor integrated circuit is on standby. Japanese Laid-Open Publication No. 6-29834 discloses a logic circuit which includes devices having a high threshold voltage as well as devices having a low threshold voltage, so that a leakage current in a semiconductor integrated circuit including such a logic circuit is decreased when the semiconductor integrated circuit is on standby. An embodiment of this conventional technology is described below with reference to FIG. 10.
FIG. 10 is a circuit diagram illustrating a schematic structure of a conventional semiconductor integrated circuit. The conventional semiconductor integrated circuit includes an inverter logic circuit I100. The inverter logic circuit I100 is connected to a drain of a PMOSFET m100 at its high potential power terminal and is connected to a drain of an NMOSFET m101 at its low potential power terminal. A source of the PMOSFET m100 is connected to a power line Vdd and a source of the NMOSFET m101 is connected to a ground line GND. The PMOSFET m100 receives a control signal CSB at its gate. The NMOSFET m101 receives a control signal CS at its gate. The control signal CS is generated by inverting the control signal CSB.
The inverter logic circuit I100 includes MOSFETs (not shown) having a low threshold voltage so as to operate the inverter logic circuit I100 at a low voltage. A threshold voltage of each of the PMOSFET m100 and the NMOSFET m101 is high. In the inverter logic circuit I100, which is on standby, when a HIGH-state control signal CS and a LOW-state control signal CSB are input to the PMOSFET m100 and the NMOSFET m101, respectively, both of the PMOSFET m100 and the NMOSFET m101 are turned on. At this point, the inverter logic circuit I100 is electrically connected via the PMOSFET m100 to the power line Vdd and is electrically connected via the NMOSFET m101 to the ground line GND. The inverter logic circuit I100 is operated at a low power voltage since the inverter logic circuit I100 includes the MOSFETs having a low threshold voltage.
In the inverter logic circuit I100, which is on standby, when the LOW-state control signal CS and the HIGH-state control signal CSB are input to the PMOSFET m100 and the NMOSFET m101, respectively, both of the PMOSFET m100 and the NMOSFET m101 are turned off. At this point, the inverter logic circuit I100 is electrically disconnected from the power line Vdd and the ground line GND, so that the inverter logic circuit I100 is not operated. A leakage current in the inverter logic circuit I100 is kept low since the threshold voltage of each of the PMOSFET m100 and the NMOSFET m101a is low.
Next, referring to FIG. 11, a conventional technology for controlling a substrate potential of a SOI (silicon on insulator) device so as to operate the SOI device at a low voltage and keep a low leakage current in the SOI device is described below.
FIG. 11 is a circuit diagram illustrating a conventional inverter logic circuit. This conventional inverter logic circuit includes a PMOSFET m102 and an NMOSFET m103. A source of the PMOSFET m102 is connected to a power line Vdd. A gate of the PMOSFET m102 and a gate of the NMOSFET m103 are connected to each other and an input terminal S1 of the conventional inverter logic circuit. A drain of the PMOSFET m102 and a drain of the NMOSFET m103 are connected to each other and an output terminal S2 of the conventional inverter logic circuit. A body (or a backgate when the conventional inverter logic circuit has a bulk structure) of the PMOSFET m102 is connected to the input terminal S1.
A source of the NMOSFET m103 is connected to a ground line GND. The gate of the NMOSFET m103 is connected to the input terminal S1. The drain of the NMOSFET m103 is connected to the drain of the PMOSFET m102 and the output terminal S2. A body (or a backgate when the conventional inverter logic circuit has a bulk structure) of the NMOSFET m103 is connected to the input terminal S1.
When a state of a control signal input via the input terminal S1 is changed from LOW to HIGH, a body (substrate) potential of the NMOSFET m103 is also changed from LOW to HIGH, so that a threshold voltage of the NMOSFET m103 is decreased. Thus, the NMOSFET m103 is rapidly turned on and is operated at high speed.
In this case, a gate potential and a body potential of the PMOSFET m102 are changed from LOW to HIGH, and the PMOSFET m102 is turned off, so that a threshold voltage of the PMOSFET m102 is increased. Similarly, when a state of a control signal input to the PMOSFET m102 is changed from HIGH to LOW, a body potential of the PMOSFET m102 is changed from LOW to HIGH, so that a threshold voltage of the PMOSFET m102 is decreased. Thus, the PMOSFET m102 is rapidly turned on and is operated at high speed.
In this case, a gate potential and a body potential of the NMOSFET m103 are changed from HIGH to LOW, and the NMOSFET m103 is turned off, so that a threshold voltage of the NMOSFET m103 is increased. In this manner, the threshold voltage of each of the PMOSFET m102 and the NMOSFET m103 is decreased when the PMOSFET m102 and the NMOSFET m103 are turned on and is increased when the PMOSFET m102 and the NMOSFET m103 are turned off, and thus the SOI device can be operated at a low voltage, and a leakage current in the SOI device can be kept low.
However, the above-described conventional technologies have the following problems.
In the conventional technology described with reference to FIG. 10, it is necessary to include MOSFETs having a high threshold voltage in the semiconductor integrated circuit in order to decrease a leakage current in the semiconductor integrated circuit when the semiconductor integrated circuit is on standby. Specifically, in order to operate the semiconductor integrated circuit at a low voltage and maintain a low leakage current in the semiconductor integrated circuit, it is necessary to form MOSFETs, each operable at a threshold voltage differing from that of the other, on the same semiconductor substrate. However, this results in a complicated production process of the semiconductor integrated circuit. Moreover, a control signal is required to be input to the semiconductor integrated circuit so as to cause the semiconductor integrated circuit to be on standby, and when the semiconductor integrated circuit is on standby, a logic circuit provided in the semiconductor integrated circuit is electrically disconnected from a power source and is not operated. Therefore, it is not appropriate to apply the conventional technology to a circuit (e.g., a flip-flop circuit, a memory, etc.) for storing data.
In the conventional technology described with reference to FIG. 11, it is necessary to provide electrodes connected to MOSFET bodies in the semiconductor integrated circuit in order to change a body potential of the MOSFETs, and thus a total area of the semiconductor integrated circuit is increased. Since it is necessary to control the body potential of the MOSFETs, this conventional technology can only be applied to PD-type (partial depletion-type) FETs and cannot be applied to FD-type (full depletion-type) FETs.
A semiconductor integrated circuit according to the present invention has the following features for solving the above-described problems of the conventional technologies.
(1) A semiconductor integrated circuit according to the present invention includes MOSFETs of at least one of N channel- and P channel-types where at least two MOSFETs included in a plurality of MOSFETs, which are provided in a channel between a high potential power line and a low potential power line, includes two serially-connected MOSFETs of the same channel-type in which their respective gates are connected to each other.
In the above-described structure, the semiconductor integrated circuit includes MOSFETs of at least one of N channel- and P channel-types where at least two MOSFETs included in a plurality of MOSFETs, which are provided in a channel between a high potential power line and a low potential power line, includes two serially-connected MOSFETs of the same channel-type in which their respective gates are connected to each other.
Accordingly, a leakage current flowing through the semiconductor integrated circuit can be greatly decreased, so that a leakage current in the semiconductor integrated circuit, when not in operation, can be decreased. Moreover, the leakage current flowing through the semiconductor integrated circuit can be decreased even if the semiconductor integrated circuit is produced by an ordinary integrated circuit production process without requiring any specific step, e.g., a step for adding MOSFETs, which operate at a high threshold voltage, to the semiconductor integrated circuit, a step for controlling a substrate voltage so as to change a threshold voltage of MOSFETs, etc. In this case, the semiconductor integrated circuit includes only FETs having an extremely low threshold voltage, and thus the semiconductor integrated circuit can be stably operated at an extremely low power voltage.
(2) The semiconductor integrated circuit according to the present invention may include a circuit which includes at least two MOSFETs of the same channel-type where the circuit is any one of a logic circuit, a data storing circuit, and a buffer circuit included in a pass transistor logic circuit.
In the above-described structure, the semiconductor integrated circuit includes any one of a logic circuit, a data storing circuit, and a buffer circuit included in a pass transistor logic circuit, and a circuit to be included in the semiconductor integrated circuit includes at least two serially-connected MOSFETs having the same channel-type in which their respective gate electrodes are connected to each other.
Accordingly, a leakage current flowing through the semiconductor integrated circuit can be greatly decreased, so that a leakage current in the semiconductor integrated circuit, when not in operation, can be decreased. Moreover, no specific signal is required for causing the semiconductor integrated circuit to be placed on standby. Moreover, the semiconductor integrated circuit includes MOSFETs which operate at an extremely low threshold voltage, and thus no additional specific circuitry is used in the semiconductor integrated circuit. Accordingly, the semiconductor integrated circuit can be operated at an extremely low voltage so as to retain data.
(3) In the semiconductor integrated circuit according to the present invention, a gate length of each of the two MOSFETs of the same channel-type may be longer than respective gate lengths of other MOSFETs included in the plurality of MOSFETs provided in the channel.
In the above-described structure, the semiconductor integrated circuit includes two MOSFETs of the same channel-type each having a gate length which is longer than respective gate lengths of other MOSFETs included in the plurality of MOSFETs provided in the channel, and the two MOSFETs of the same channel-type are serially connected such that their respective gate electrodes are connected to each other.
Accordingly, a leakage current which may flow through the semiconductor integrated circuit can be decreased.
(4) A semiconductor integrated circuit according to the present invention includes MOSFETs of at least one type of N channel- and P channel-types where at least one set of MOSFETs included in a plurality of MOSFETs, which are provided in a channel between a high potential power line and a low potential power line, includes first through third MOSFETs of the same channel-type, the first through third MOSFETs being serially connected, respective gate electrodes of the first and third MOSFETs being connected to each other, and a gate electrode of the second MOSFET being connected to a section of the semiconductor integrated circuit which has a sufficient potential to turn on the second MOSFET.
In the above-described structure, the semiconductor integrated circuit includes MOSFETs of at least one type of N channel- and P channel-types where at least one set of MOSFETs included in a plurality of MOSFETs, which are provided in a channel between a high potential power line and a low potential power line, includes first through third MOSFETs having the same channel-type, the first through third MOSFETs being serially connected, respective gate electrodes of the first and third MOSFETs being connected to each other, and a gate electrode of the second MOSFET being connected to a section of the semiconductor integrated circuit which has a sufficient potential to turn on the second MOSFET.
Accordingly, the first MOSFET has load resistances provided by the second and third MOSFETs, and thus a leakage current flowing through the semiconductor integrated circuit can be extremely low. Moreover, the leakage current flowing through the semiconductor integrated circuit can be decreased even if the semiconductor integrated circuit is produced by an ordinary integrated circuit production process without requiring any additional specific steps, e.g., a step for adding MOSFETs which operate at a high threshold voltage to the semiconductor integrated circuit, and a step for controlling a substrate voltage so as to change a threshold voltage of the MOSFETs. In this case, the semiconductor integrated circuit includes only FETs having a threshold voltage which is extremely low, and thus the semiconductor integrated circuit can be stably operated at an extremely low power voltage.
(5) A semiconductor integrated circuit according to the present invention includes MOSFETs of at least one of N channel- and P channel-types where at least one set of MOSFETs included in a plurality of MOSFETs, which are provided in a channel between a high potential power line and a low potential power line, includes first through third MOSFETs of the same channel-type, the first through third MOSFETs being serially connected, respective gate electrodes of the first and third MOSFETs being connected to each other, and a gate electrode of the second MOSFET receiving a control signal differing from that input to the respective gate electrodes of the first and third MOSFETs.
In the above-described structure, the semiconductor integrated circuit includes MOSFETs of at least one of N channel- and P channel-types where at least one set of MOSFETs included in a plurality of MOSFETs, which are provided in a channel between a high potential power line and a low potential power line, includes first through third MOSFETs having the same channel-type, the first through third MOSFETs being serially connected, respective gate electrodes of the first and third MOSFETs being connected to each other, and a gate electrode of the second MOSFET receiving a control signal differing from that input to the respective gate electrodes of the first and third MOSFETs.
Accordingly, the first MOSFET has load resistances provided by the second and third MOSFETs, and thus a leakage current flowing through the semiconductor integrated circuit can be extremely low. Moreover, the leakage current flowing through the semiconductor integrated circuit can be decreased even if the semiconductor integrated circuit is produced by an ordinary integrated circuit production process without requiring any additional specific steps, e.g., a step for adding MOSFETs which operate at a high threshold voltage to the semiconductor integrated circuit, and a step for controlling a substrate voltage so as to change a threshold voltage of the MOSFETs. In this case, the semiconductor integrated circuit includes only FETs having a threshold voltage which is extremely low, and thus the semiconductor integrated circuit can be stably operated at an extremely low power voltage.
(6) The semiconductor integrated circuit according to the present invention may include a circuit which includes at least one set of the first through third MOSFETs of the same channel-type where the circuit is any one of a logic circuit, a data storing circuit, and a buffer circuit included in a pass transistor logic circuit.
In the above-described structure, the semiconductor integrated circuit includes a circuit which includes at least one set of the first through third MOSFETs having the same channel-type, in which the circuit is any one of a logic circuit, a data storing circuit, and a buffer circuit included in a pass transistor logic circuit.
Accordingly, a leakage current flowing through the semiconductor integrated circuit can be greatly decreased, so that a leakage current in the semiconductor integrated circuit, when not in operation, can be decreased. Moreover, no specific signal is required for causing the semiconductor integrated circuit to be placed on standby. Moreover, the semiconductor integrated circuit includes MOSFETs which operate at an extremely low threshold voltage, and thus no additional specific circuitry is used in the semiconductor integrated circuit. Accordingly, the semiconductor integrated circuit can be operated at an extremely low voltage so as to retain data.
(7) In the semiconductor integrated circuit according to the present invnetion, a gate length of the second MOSFET may be longer than respective gate lengths of the first and third MOSFETs included in the plurality of MOSFETs provided in the channel.
In the above-described structure of the semiconductor integrated circuit, a gate length of the second MOSFET is longer than respective gate lengths of the first and third MOSFETs included in the plurality of MOSFETs provided in the channel.
Accordingly, even if the respective gate lengths of the first and third MOSFETs are not increased, a leakage current flowing through the semiconductor integrated circuit can be decreased by adjusting the gate length of the second MOSFET.
(8) The semiconductor integrated circuit according to the present invention may be formed on a SOI substrate.
The semiconductor integrated circuit according to the present invention is formed on a SOI substrate.
Accordingly, the present invention is highly advantageous as a technology for realizing a circuit which is operated at low voltage and has a low leakage current without performing threshold control by substrate bias control or without using a multi-threshold device technology in which a high threshold device is additionally used for a circuit including such a device to have low leakage current characteristics.
Thus, the invention described herein makes possible the advantages of providing a semiconductor integrated circuit which can be produced by a simple production process, rather than a complicated production process, but can be operated at low voltage and in which a leakage current can be kept low when the semiconductor integrated circuit is on standby.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.